Integrated circuit testing is critical at both the design level to confirm proper operation of a given design and at the manufacturing level for ensuring a given chip meets all manufacturing specifications prior to shipment. However, as the cost of integrated circuit fabrication continues to fall, the cost of integrated circuit testing has increased. One reason for increasing test costs is based on the increasing ratio of number of transistors to number of implementable pads on an integrated circuit. For example, the ratio of the number of transistors to number of pads increased from 2,500 in 1990 to 300,000 in 2001. Undoubtedly, this trend for smaller and smaller integrated circuits with increasing transistor density will continue. The increasing trend to integrate greater capability into IC's, resulting in embedded complexities, has significantly reduced the effectiveness of the present in-circuit testing methods at the board level via a “bed of nails” interface. Due to the physical limitations of external test probes in terms of required size and spacing, the number of external pads is likely to decrease rather than increase, and will certainly not keep up with the rate of increase in number of integrated circuit transistors.
Accordingly, alternative solutions to current integrated circuit test techniques are continually being sought. The most popular trends in improving testability of integrated circuits include Design for Test (DFT) and Concurrent Test (CCT) techniques. DFT techniques are general design procedures, practices and rules that fit or link circuit testability to the development of manufacturing environments. DFT requires the addition of specialized test hardware on the integrated circuit itself that is independent of the blocks implementing the intended functionality of the integrated circuit. Traditional DFT techniques include Scan Techniques (for example, using the IEEE 1149.1 Boundary Scan and Joint Test Access Standard (JTAG) protocols), Built In Self Test (BIST), and IDDQ tests.
CCT techniques allow independent and concurrent testing (i.e., testing in parallel) of independent functional blocks on the integrated circuit. CCT techniques rely on partitioning the functionality of the overall intended integrated circuit functionality into independently testable functional blocks during the design phase. For example, there is an increasing trend to building System-on-a-Chip (SOC) integrated circuits which are devices made up of multiple independent cores that each provide specific independent functionality. The SOC cores are often supplied by various third parties, and are “stitched” together with customized “glue” logic to meet the overall design goals of the particular SOC. SOCs are prime candidates for implementing DFT and CCT testing techniques.
During testing, the integrated circuit is placed into a test mode that is different from its normal operating mode. When in test mode, test data is routed to the functional blocks under the control of the DFT specialized test hardware rather than from external integrated circuit pads (i.e., the DFT hardware replaces the I/O pins for data/address/control I/O signals). The DFT hardware applies test data to the block under test, and receives return results. Analysis of the result data may be performed by the DFT hardware, or may be output to an external tester device for off-line analysis.
DFT hardware is typically designed to reduce the number of full functional test channels (and therefore physical test probes) required for test access. This is achieved using various techniques. In Scan testing, a scan storage cell is implemented for each input and output of interest of the block under test. The scan storage cells are connected together in a serial chain, which is connected at an input to the integrated circuit's scan-in port and connected at an output to the integrated circuits scan-out port. Test data is loaded into the scan chains via a serial scan load operation, for example using the IEEE 1149.1 Boundary Scan and JTAG protocols, incorporated herein by reference for all that it teaches. The scan storage cells are multiplexed with the data path used during normal operation of the integrated circuit such that when the integrated circuit is placed in test mode, data is applied to the inputs and outputs of interest of the block under test from respective scan storage cells, and when the integrated circuit is placed in normal operating mode, data is applied to the inputs and outputs of the block under test via the normal data path (typically from an I/O pin or an I/O signal from another functional block on the integrated circuit). In the standard JTAG protocol, data is loaded into the scan chains via a Test Data In (TDI) serial input pin, and data is output from the scan chains via a Test Data Out (TDO) serial output pin. Accordingly, access to any number of I/O ports within the integrated circuit is made available via only four test pins (TDI, TDO, TCK (i.e., Test Clock, for receiving a clock signal used to step the TAP controller state machine and to serially load/unload data), and TMS (i.e., Test Mode Select, for allowing command control of the JTAG circuitry).
Another technique that may be used independent of or along with Scan techniques is known as Built In Functional Test, or BIST. BIST includes hardware that allows the integrated circuit to test itself. BIST hardware typically includes test pattern generators (TPGs), output response analyzers (ORAs), and/or microdiagnostic routines. There are several types of BIST, including on-line BIST that refers to testing that occurs during normal functional operating conditions (i.e., the integrated circuit is not placed into a test mode), generic off-line BIST where testing occurs when the integrated circuit is placed into test mode, functional off-line BIST which deals with the execution of a test based on a functional description of the block under test, and structural off-line BIST that refers to testing in order to detect structural faults.
Yet another technique that may be used independent of or along with Scan techniques and/or BIST is data compression, such as X-Mode. In this technique, test data input to the DFT structures is compressed and results are compressed prior to sending them to the outside world.
In each of the above techniques, the focus is on reducing test access pin count. However, because data must be applied serially to the integrated circuit, it increases test time, and therefore test cost.
Concurrent testing (CCT) and compression techniques assist in reducing test time. As described above, CCT allows multiple independent functional blocks to be tested in parallel, and compression techniques reduce the volume of data to be transferred to and from the integrated circuit under test.
However, in each of the above techniques, the cost of test is still high because currently, expensive “bed-of-nails” testers are still used to probe the test access points on the integrated circuits under test. In each of the above-described techniques, the integrated circuit designs typically feature centralized or decentralized Test Access Mechanisms (TAM) through which data passes. In a traditional DFT test, these TAMs receive test data from chip pins or pads connected directly to tester resources.
FIG. 1 illustrates a simplified example of an integrated circuit chip 10 employing DFT techniques. The chip 10 includes one or more digital blocks 12a, 12b, each having associated DFT hardware 16a, 16b that facilitates testing of the digital blocks 12a, 12b, and a Test Access Mechanism (TAM) 14. The TAM 14 receives test data via integrated circuit chip pins 15a, 15b that are connected directly to tester resources 18a, 18b in a traditional “bed-of-nails” tester 20.
DFT techniques suffer from several common limitations. One typical difficulty is that DFT often requires a large amount of memory for storing test data. While BIST overcomes this problem by including test pattern generators for generating predictable patterns of test data without storing it, standard BIST techniques are typically covered by BIST intellectual property, which can be expensive to purchase and uses precious space on the chip.
Ideally, wafer, package, subsystem and system level DFT approaches should entail structures that provide a means for testing at critical locations within the integrated circuits, PC boards and systems. Pertinent data feedback over the life of the product to all levels of the process would enhance continuous improvement and project future requirements amidst increasing complexities.
Accordingly, it would be desirable to overcome the problems of the prior art described above, by providing an integrated circuit testing technique that reduces the required integrated circuit test pin/pad count, decreases test time, and is economical.